Since the number of CPU cores grows significantly nowadays, the demand of hardware partitioning has become evident. Hardware partitioning could improve the security, multi-task ability and resource efficiency of each CPU. In this paper, we’d like to share Wiwynn’s concept of Hardware Partitioning (HPAR) architecture, which can be implemented in multiple CPUs system with single DC-SCM. With assistant BMC’s help, BMC has the access to each CPU and dual socket system can boot up as either single or dual node. The HPAR method creates strict boundaries between each socket, which reduces the risk of unauthorized access or data leakage between partitions. Also, each partition can perform different tasks on one system simultaneously, optimizing the hardware utilization by segmenting workloads.
